In a photolithography process for manufacturing semiconductor devices and liquid crystal displays (LCD's), resist is coated on a substrate, and the resultant photoresist coating film is exposed to light and developed. The series of processing stages are carried out in a coating/developing processing system having discrete heating sections, where each heating section incorporates a hotplate with a built-in heater of a resistance heating type.
Feature sizes of semiconductor device circuits have been reduced to less than 0.1 microns. Typically, the pattern wiring that interconnects individual device circuits is formed with sub-micron line widths. To provide reproducible and accurate feature sizes and line widths, it is strongly desired to control more accurately the heat-treatment temperature of the photoresist film. The substrates or wafers are usually treated or processed using the same process recipe (i.e., individual treatment program) in units (i.e., lots or batches) each consisting of, for example, twenty-five wafers. Individual process recipes define heat-treatment conditions under which the heat-treating is performed. Wafers belonging to the same lot are usually heated under the same conditions.
Post exposure bake (PEB) plays an important role in photoresist processing. Heat-treating a photoresist may have many purposes, from removing a solvent from the photoresist to catalyzing chemical amplification in the photoresist. In addition to the intended results, heat-treating may cause numerous problems. For example, the light sensitive component of the photoresist may decompose at temperatures typically used to remove the solvent, which is an extremely serious concern for a chemically amplified resist (CAR) since the remaining solvent content has a strong impact on the diffusion and amplification rates. In addition, heat-treating can affect the dissolution properties of the resist and thus have direct influence on the developed resist profile. CAR's are particularly sensitive to temperature variations during heat-treatment and temperature variations can result in variations in critical dimensions (CDs) across a wafer surface.
Often, temperature variations in heat-treating processes such as PEB are monitored and corrected by heat-treating resist coated test wafers (non-manufacturing wafers) on a regular basis, measuring CDs of the resulting structures formed on the test wafers, and adjusting the temperature of the hotplate. The use of non-production test wafers has important disadvantages that include manufacturing down time, limited information and test accuracy acquired from the test wafers due to few test wafer runs and therefore small amount of data, and short-term temperature deviations that may go unnoticed due to long intervals between test wafer runs. Similarly, test wafers that contain temperature sensors (e.g., thermocouples) can only be run infrequently and subsequently any temperature adjustments made using the temperature sensor data must be confirmed by measuring CDs on processed test wafers.
Therefore, new methods are required for monitoring and controlling heat-treating of resist coated wafers that can provide the high metrology data density required for optimizing a heat-treating process, while allowing for high wafer throughput.